app / stack designer
engine 0.1, data 2026.09.05-1

Stack designer

Case C-0412. Layer order, CTE staircase and per-interface stress against the 0.3 / 0.8 / 2.0 GPa thresholds. Headline numbers come from the engine; the layer table and per-interface bars are a mock layout pending the discrete stack engine.

CTE staircase

mock layout, R05 steps in proportion to 1 / M
58111417CTEAl2O3MoO2s1s2s3s4s5CrNiCrIN718

Interface stress

mock bars, GPa at dT 1 200 K
0.000.250.500.751.00Al2O3 / MoO20.12MoO2 / step 10.61step 1 / step 20.63step 2 / step 30.58step 3 / step 40.55step 4 / step 50.49step 5 / Cr0.20Cr / NiCr0.31NiCr / IN7180.22
direct joint, R04
2.92 GPa
equal CTE steps mock
1.12 GPa
minimax step stress, R05
0.63 GPa
Phi, R06
0.79
fracture margin at step 1, R18
36.7
membrane gate, R24
passes

Layers, top to bottom

mock layer table, total 3.7 µm between substrate and build
LayerRolet, µmCTEM, GPa
Al2O3, c-planesubstratebulk7.0580
MoO2 adhesionanchor6.5400
Step 1, Mo 85 wt%graded6.9445
Step 2, Mo 70 wt%graded8.4415
Step 3, Mo 54 wt%graded10.1383
Step 4, Mo 38 wt%graded11.9350
Step 5, Mo 20 wt%graded13.8315
Cr barrierbarrier6.2353
NiCr seedseed13.0290
IN718, LPBFbuildbulk15.5282

CTE in 1e-6 / K. M is the biaxial modulus E / (1 - nu), rule R01. Edit thickness and re-run to update G at each interface (R16).

Activity0 / 15 steps
mock: simulated measurement. quality C: placeholder value, to verifyR00 to R24